1. Field of the Invention
The present invention relates to techniques for semiconductor device manufacturing. More specifically, the present invention relates to a method for improving device qualities by etching sidewalls of semiconductor devices formed on isolated mesas of a partitioned substrate.
2. Related Art
Solid-state light-emitting devices are expected to lead the next wave of illumination technologies. High-brightness light-emitting diodes (HB-LEDs) are emerging in an increasing number of applications, from light source for display devices to light-bulb replacement for conventional lighting. Meanwhile, solid-state lasers continue to beam as the driving force in many critical technological fields, from optical data storage, to optical communication networks, and to medical applications.
In recent years, an increasing demand has emerged for short wavelength light-emitting devices, such as blue and UV LEDs and diode lasers. These short wavelength light-emitting devices are generally based on wide band-gap semiconductor materials, such as the nitride-based InxGayAl1-x-yN (0<=x<=1, 0<=y<=1) materials and zinc oxide-based ZnxMgyCd1-x-yO (0<=x<=1, 0<=y<=1) materials, which both are under intense development worldwide. In particular, recent success in the development of nitride-based LEDs and lasers (e.g., GaN-based LEDs and lasers) not only extends the light-emission spectrum to the green, blue, and ultraviolet region, but also can achieve high light emission efficiency, low power consumption, and long operation lifetime.
GaN-based single-crystal substrates however are not commercially available in large quantities. Consequently, other substrate materials, such as silicon (Si), sapphire (Al2O3), gallium arsenide (GaAs), and silicon carbide (SiC), are often used as supporting substrates for epitaxial growth of GaN-based semiconductor devices. The heterogeneity between the substrate and the semiconductor devices causes inevitable lattice-constant and thermal-expansion coefficient mismatches. As a result, qualities of these nitride-based semiconductor devices, such as light emitting efficiency and reliability, can be significantly impacted by such mismatches. In particular, the above mismatches can result in high density of dislocations and large in-plane stresses in the epitaxial layers, which can subsequently lead to device quality deterioration and high probability of cracking of the multilayer structures.
A number of techniques have been introduced to effectively reduce the dislocation density due to the lattice-constant mismatch, for example, by using a buffer layer between the heterogeneous substrate and epitaxial semiconductor layers, or by using an epitaxial lateral overgrowth (ELOG) technique. However, these techniques still exhibit deficiencies in eliminating stresses caused by the above mismatches, and cracking in the epitaxial semiconductor layers continues to be a serious problem during fabrication.
A recently proposed technique can effectively reduce in-plane stresses by “partitioning” a large wafer into individual independent platforms. Note that “partitioning” the wafer is referred to the process of patterning and forming intersection trenches on the wafer surface without breaking the wafer. Typically, deep trenches are patterned and formed (e.g., by etching the substrate) on a flat substrate surface, which divide the substrate surface into isolated “islands” surrounded by trenches. Next, semiconductor multilayer structures are fabricated on the partitioned substrate, and individual devices are formed on isolated single-unit platforms. Because the stress force is proportional to surface area, the stress in each isolated device is significantly reduced and limited.
A problem arises from growing semiconductor multilayer structures on these individual deposition platforms. Each platform corresponds to a relatively confined area for film growth, and the boundaries of each platform can have deleterious effect on the multilayer structure near the boundary.
Hence, what is needed is a method and an apparatus that can obtain high-quality boundaries for multilayer semiconductor devices which are fabricated on isolated platforms without the above-described problems.